Freescale Semiconductor /MK61F15WS /LPTMR0 /PSR

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Interpret as PSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)PCS0 (0)PBYP 0 (0000)PRESCALE 0RESERVED

PBYP=0, PCS=00, PRESCALE=0000

Description

Low Power Timer Prescale Register

Fields

PCS

Prescaler Clock Select

0 (00): Prescaler/glitch filter clock 0 selected.

1 (01): Prescaler/glitch filter clock 1 selected.

2 (10): Prescaler/glitch filter clock 2 selected.

3 (11): Prescaler/glitch filter clock 3 selected.

PBYP

Prescaler Bypass

0 (0): Prescaler/glitch filter is enabled.

1 (1): Prescaler/glitch filter is bypassed.

PRESCALE

Prescale Value

0 (0000): Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.

1 (0001): Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.

2 (0010): Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.

3 (0011): Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.

4 (0100): Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.

5 (0101): Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.

6 (0110): Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.

7 (0111): Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.

8 (1000): Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.

9 (1001): Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.

10 (1010): Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.

11 (1011): Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.

12 (1100): Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.

13 (1101): Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.

14 (1110): Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.

15 (1111): Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

RESERVED

no description available

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